The use of risk assessment to support control of Salmonella in pork

Salmonella is one of the major zoonotic foodborne pathogens worldwide and pork products have been identified among the main sources of salmonellosis in humans. In some countries, like Brazil, relatively high prevalences may be found in pig herds and among carcasses at slaughter (Schwarz et al. 2010). In Denmark, a contingency plan has been in place but nevertheless domestic pork is still estimated to be the most important food source for salmonellosis, as it is in the EU as a whole (Anonymous 2015). Therefore, there is a continued focus on the identification of effective intervention measures in the pig and pork production chain. In this keynote, an overview will be given of some research projects that have been performed to study the potentials of interventions in the pork production chain. The specific objective in these projects was to estimate their effectivity in terms of reduction of the public health risk of salmonellosis. The results illustrate how a quantitative microbiological risk assessments (QMRAs) approach can be applied to support the control of Salmonella in pork

The impact of CMOS scaling projected on a 6b full-Nyquist non-calibrated flash ADC

A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties;\ud a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design